1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication. More particularly, the present invention relates to a method of fabricating a photodiode integrated with MOS devices.
2. Description of the Related Art
FIGS. 1A-1H are cross-sectional diagrams schematically illustrating a series of conventional process steps used to fabricate a photodiode, an NMOS transistor and a PMOS transistor, which are all integrated together onto a semiconductor substrate 100. Above the semiconductor substrate 100, three active regions 10-12 are defined for the arrangement of the photodiode, NMOS transistor and PMOS transistor, respectively. In the drawings, three well regions 100A, 100B and 100C are formed in the semiconductor substrate 100 within the respective active regions 10, 11 and 12. Note that the well regions 100A and 100B are P-wells and the well region 100C is an N-well.
As shown in FIG. 1A, a gate insulator 101 is formed along the entire surface of the semiconductor substrate 100 and then three gates 102, 103 and 104 are deposited above the gate insulator 101 but positioned within the active regions 10, 11 and 12, respectively. Next, the active region 12 is masked with a photoresist layer 105, and then N-type dopants 106 are introduced by ion implantation throughout the active regions 10 and 11, but not under the gates 102 and 103, so as to form N-type lightly-doped regions 107 and 108, as shown in FIG. 1B. Accordingly, a P/N junction is constructed between the well region 100A and the N-type doped region 107 to be the photodiode. The photoresist layer 105 is thereafter removed.
Referring to FIG. 1C, the active regions 10 and 11 are masked with a photoresist layer 109, and P-type dopants 110 are introduced by ion implantation throughout the active region 12, but not under the gate 104, to form P-type lightly-doped regions 111. Next, as shown in FIG. 1D, an insulating layer 112 is conformably deposited over the entire surface of the substrate 100. Then, the insulating layer 115 is etched back to sidewall spacers 113, 114 and 115 on the sidewalls of the gates 102, 103 and 104, respectively. The resulting cross-sectional view is FIG. 1E.
Then, the active regions 10 and 12 are masked by a photoresist layer 116 as shown in FIG. 1E Subsequently, N-type dopants 117 are introduced by ion implantation throughout the active region 11, but not under the gate 103 or the sidewall spacers 114, therefore to form N-type heavily-doped regions 118 while merging with a portion of the N-type lightly-doped regions 108. The photoresist layer 116 is thereafter removed.
Next, the active regions 10 and 11 are masked by a photoresist layer 119 as shown in FIG. 1G. Subsequently, P-type dopants 120 are introduced by ion implantation throughout the third active region 12, but not under the gate 104 or the sidewall spacers 115, to form P-type heavily-doped regions 121 while merging with a portion of the P-type doped regions 111. The photoresist layer 119 is thereafter removed and the resulting cross-sectional view is FIG. 1H.
However, the doping concentration of the doped regions 107, which constitute the cathode of the photodiode, is determined in the formation of the light-doped regions 108 for the NMOS transistor. Thus, the prior art is useful only in the circumstance that the required doping concentrations for the doped regions 107 and 108 are substantially the same. Moreover, while converting the insulating layer 112 to the sidewall spacers 113-115, the surface of the doped regions 107 would suffer from etching damage and therefore increase the junction leakage current for the photodiode.